1. Field of the Invention
The present invention relates to a driving circuit of a display panel, and more particularly, to an address energy recovery circuit.
2. Discussion of the Related Art
FIG. 1 shows a conventional structure of a 3-electrode surface discharging type alternating current (AC) plasma display panel (PDP). Referring to FIG. 1, a PDP 1 includes a front glass substrate 100 and a rear glass substrate 106. Address electrode lines A1, A2, . . . , Am, upper and lower dielectric layers 102 and 110, Y electrode lines Y1, . . . , Yn, X electrode lines X1, . . . , Xn, a phosphor layer 112, a barrier rib 114, and an MgO protective layer 104 are disposed between the front and rear glass substrates 100 and 106.
The address electrode lines A1, . . . , Am are formed in a predetermined pattern on the rear glass substrate 106 and covered with the lower dielectric layer 110. The barrier ribs 114 are formed on the lower dielectric layer 110 in parallel to the address electrode lines A1, . . . , Am, and they divide a discharging region of each display cell and prevent optical cross talk between cells. The phosphor layer 112 is formed on the lower dielectric layer 110 and the sides of the barrier ribs 114.
The X electrode lines X1, . . . , Xn and the Y electrode lines Y1, . . . , Yn are formed on a lower surface of the front glass substrate 100 orthogonally to the address electrode lines A1, . . . , Am. An X and Y electrode pair cross with an address electrode to form a display cell. The X electrode lines X1, . . . , Xn and the Y electrode lines Y1, . . . , Yn may include transparent electrode lines Xna and Yna, made of transparent conductive materials such as indium tin oxide (ITO), and metal electrode lines Xnb and Ynb, which improve electrode line conductivity. The upper dielectric layer 102 covers the X electrode lines X1, . . . , Xn and the Y electrode lines Y1, . . . , Yn. The protective layer 104 is formed on the upper dielectric layer 102 to protect the panel 1 from a strong electric field. A plasma forming gas is filled in the discharging space 108.
A typical driving method for the above AC PDP includes an initialization process, an addressing process, and a display sustain process sequentially performed in a unit sub-field. The initialization process provides uniform states of electric charges of the display cells that will be driven. The addressing process provides desired charges for selected and non-selected cells. In the display sustain process, discharging operations are performed in the selected cells. Here, discharging operations generate plasma, which emits ultraviolet rays that excite the phosphor layers 112, thereby generating visible light to display an image.
In this case, a plurality of unit sub-fields are included in a unit frame, and a desired gray level may be displayed by the display sustain time of the sub-fields.
FIG. 2 shows a general driving apparatus in the PDP 1 shown in FIG. 1.
Referring to FIG. 2, the driving apparatus of the PDP 1 includes an image processor 200, a logic controller 202, an address driver 206, an X driver 208, and a Y driver 204. The image processor 200 generates internal image signals, such as 8 bit red (R), green (G), and blue (B) color image data, a clock signal, and vertical and horizontal synchronization signals. The logic controller 202 generates driving control signals SA, SX, and SY. The address driver 206 processes the address control signal SA to generate address signals, and applies the address signals to the address electrode lines A1, . . . , Am. The X driver 208 processes the X driving control signal SX and applies it to the X electrode lines X1 . . . Xn. The Y driver 204 processes the Y driving control signal SY and applies it to the Y electrode lines Y1 . . . Yn.
FIG. 3 is a circuit diagram showing an example of the address driver 206 of FIG. 2. Referring to FIG. 3, the address driver 206 generates address signals SA1, . . . , SAm by processing the address control signal SA input from the logic controller 202. The address control signal SA includes upper control signals A1U . . . AmU, for switching upper switches F1U . . . FmU, and lower control signals A1L . . . AmL, for switching lower switches F1L . . . FmL. The upper and lower switches F1U . . . FmU and F1L . . . FmL are connected to the address electrodes A1 . . . Am, which are first electrodes of panel capacitors Cp1 . . . Cpm, respectively. The upper switches F1U . . . FmU are also connected to an address power source Va. The lower switches F1L . . . FmL are also connected to ground.
FIG. 4 shows a typical address-display separation (ADS) driving method for the Y electrode lines in the PDP of FIG. 1.
Referring to FIG. 4, a unit frame is divided into 8 sub-fields SF1 . . . SF8 for time division gray scale display. The sub-fields SF1 . . . SF8 are further divided into reset periods (not shown), address periods A1 . . . A8, and sustain periods S1 . . . S8.
In the address periods A1 . . . A8, display data signals are applied to the address electrode lines A1 . . . Am of FIG. 1, and at the same time, scan pulses are sequentially applied to the corresponding Y electrode lines Y1 . . . Yn.
In the sustain periods S1 . . . S8, sustain discharging pulses are alternately applied to the Y electrode lines Y1 . . . Yn and the X electrode lines X1 . . . Xn to display a desired image.
The brightness of the PDP is proportional to the lengths of the sustain periods S1 . . . S8. The length of the sustain periods S1 . . . S8 in the unit frame is 255T (T is a unit time). Here, a time corresponding to 2n−1 is set for the sustain period Sn in nth sub-filed SFn. Accordingly, when the sub-fields to be displayed are selected appropriately among the 8 sub-fields, 256 gray levels may be displayed, including a zero gray level.
FIG. 5 is a timing diagram showing driving signals that may be applied to the AC PDP of FIG. 1 when utilizing the ADS method. Referring to FIG. 5, the sub-field SF includes a reset period PR, an address period PA, and a sustain period PS.
In the reset period PR, reset pulses are applied to all scan lines to initialize the wall charges for all display cells. In the address period PA, a bias voltage Ve is applied to the common electrodes X, and the scan electrodes Y1 . . . Yn and the address electrodes A1 . . . Am are turned on simultaneously to select cells for displaying an image. In the sustain period PS, sustain pulses VS are alternately applied to the common electrodes X and the scan electrodes Y1 . . . Yn, while a low level voltage VG is applied to the address electrodes A1 . . . Am.
In performing the addressing operations as shown in FIG. 4 and FIG. 5, the charges charged in the display cells at high levels are discharged through ground terminals if a next signal is at the low level. Additionally, in order to convert a display cell that is at the low level, in the previous scan line, into the high level, a power source supplies all required charges.
In other words, when addressing display cells according to the conventional driving method, available charges previously stored in an address electrode panel capacitor are not used, which unnecessarily increases power consumption. If the address operations are performed at every sub-field, unnecessary power consumption may significantly increase.